Various methods exist for packaging integrated circuit chips and mounting them on a printed circuit board. With a wire-bonding technique, the integrated circuit chip may be encapsulated, that is, as a molded plastic package or completely enclosed as a ceramic package. The chip is provided with wire-bonding pads onto which fine wires are bonded, which, in turn, have their opposite ends bonded to inner lead bond (ILB) pads contained in the package to be encapsulated. Thereafter, the chip and an end of each ILB are encapsulated in molding compound or enclosed in ceramic, with the outer lead (OL) exposed for further connections.
The integrated circuit chip's package very often has leads which are formed downwardly so that they may be soldered to the printed circuit board. In some cases, the integrated circuit chip's package plugs into a socket that makes the electrical connections on the printed circuit board.
Three-dimensional packaging techniques have been developed to increase such items as computer memory density. This can be done by stacking layers of ceramic containing multiple memory chips and stacked memory packages, such as in high-end computer memory subsystems. Such packaging methods have been carried out by mounting chips at an angle to a memory or a processor board in individual packages, or on a memory module known as a single-in-line memory module (SIMM). A dual-in-line package (DIP) is an example of such a memory package. The purpose is to put more memory into less volume. For a discussion of a three-dimensional memory cube system, see, "Evaluation of a Three-Dimensional Memory Cube System" in IEEE Transactions on Components, Hybrids, and Manufacturing Technology, Volume 16, No. 8, December 1993, pp. 1006-1011, Claude L. Bertin, David J. Perlman, and Stuart N. Shanken.
This article indicates how a thin film metal layer is added to each chip surface to transfer signal and power input and output from the chip bond pads to the chip edges. The chips may be stacked and a right-angle joint is formed between the end of a transfer tab for transferring signals in and out of each chip. Thus, it is possible to use electrical probing or to provide further interconnections on the face of the cube of the chip stack.
Accordingly, many problems exist when attempting to achieve a high density in a relatively small space. Various boundary conditions are presented when confronted with the problem of interconnecting different chip-stack heights to the printed circuit board. Such conditions include:
(1) minimum printed circuit card footprint; PA1 (2) low cost for the package and the card attachment; PA1 (3) there must be an opportunity for the provision of heat removal; PA1 (4) the reliability of the devices on the silicon integrated circuit chip must be maintained; PA1 (5) the chip stack must be protected during the bonding and assembling, the testing, and the use in the final assembly; PA1 (6) if possible, a standard card footprint developed by the Joint Electronic Devices Engineering Council (JEDEC) should be used; PA1 (7) the signal lines, power lines, and/or ground lines should be interconnected on the package's substrate, wherever possible; and PA1 (8) compatibility should be maintained, when possible, with the appropriate test and burn-in equipment.